1. Field of the Invention
This invention relates generally to systems and methods for testing memory, and more particularly to systems and methods for on-chip diagnostics using a high speed self checking loopback.
2. Description of the Related Art
Double data rate (DDR) synchronous dynamic random access memory (SDRAM) is a class of memory capable of providing approximately twice the bandwidth of single data rate SDRAM. DDR SDRAM achieves this increased bandwidth without requiring and increased clock frequency by transferring data on both the rising and falling edges of the clock signal. Because the increased bandwidth, DDR SDRAM often is used in the design of integrated circuits.
However, the high cost of manufacturing integrated circuits makes screening of finished goods from defects highly desirable. One aspect of screening is the testing of input and output interfaces on various aspects of the integrated circuit. For example, prior art techniques have been developed to test I/O interfaces for DDR memory, as illustrated next with reference to FIG. 1.
FIG. 1 is a block diagram showing a prior art daisy chain test system 100. The prior art daisy chain test system 100 generally is utilized to test the DDR interface, illustrated in FIG. 1 via the data pad 104 on the DDR memory device 102. Specifically, the prior art daisy chain test system 100 includes an external off-chip data generator 106 in communication with the data pad 104. In addition, an external off-chip comparator 110 is placed in communication with the data pad 104, and an external loopback element 108 is coupled to the output and input interfaces of the data pad 104. Generally, the external loopback element 108 comprises a simple wire that connects the output of the data pad 104 with the input of the data pad 104.
In operation, the external data generator 106 provides a bit lane of test data to the data pad 104 using a specialized test data input interface 112 of the DDR memory device 102. The specialized test data input interface 112 provides a mechanism for the test data to be provided to the DDR memory device 102 for testing purposes. Once the test data is provided to the data pad 104, the data is sent through an output data path of the data pad 104 to the external loopback element 108, which routs the test data back to the data pad 104 using an input data path of the data pad 104. Thereafter, the test is provided to the external off-chip comparator 110 via a specialized test data output interface 114 of the DDR memory device 102. The specialized test data output interface 114 provides a mechanism for the test data to be extracted from the DDR memory device 102 for testing purposes.
Thus, to test the DDR interface, the prior art daisy chain system 100 generally needs to provide test data to the DDR interface from an off-chip source, which is accomplished using the external data generator 106. Since it is desirable to test the functionality of the DDR memory device 102 interface, the test data is provided to the DDR memory device 102 prior to the output data path. Hence, as described above, a specialized test data input interface 112 generally is manufactured into the DDR memory device 102 for this purpose. Once the test data is sent through the output path and the data pad 104, the test data is looped back to the data pad 104 via the external loopback element 108. The returned test data is compared with expected values using an off-chip testing device, such as the external off-chip comparator 110 illustrated in FIG. 1. To fully test the input path, the external off-chip comparator 110 should acquire the returned test data after the input path. Hence, similar to above, a specialized test data output interface 114 generally is manufactured into the DDR memory device 102 for this purpose.
Unfortunately, since the test data is generated off-chip, timing issues can arise because of capability differences between the external off-chip data generator 106 and the DDR memory device 102. Similar issues can arise because of capability differences between the external off-chip comparator 110 and the DDR memory device 102. Moreover, the external loopback element 108 returns a single bit line of data back to the data pad. Thus, in order to fully test the device, the test generally is repeatedly run using a different data pin each time.
In view of the foregoing, there is a need for systems and methods for improved testing of DDR physical interfaces. The systems and methods should provide a mechanism to test the DDR physical interface while avoiding timing issues present when using off-chip testing equipment. The systems and methods should provide a mechanism to analyze production run modes with higher accuracy and ease.